This tutorial explains how to locate and configure the GPIO pins for input, output, pull-up, pull-down, high-z, etc.
I couldn’t find this information clearly stated in any one place, so here’s my attempt. If the TI wiki was actually a wiki that allowed people to edit it, I’m sure something like this would already be there.
Technical Reference Manual:
AM335xARM Cortex-A8Microprocessors (MPUs) Technical Reference Manual
AM335xARM Cortex-A8 Microprocessors(MPUs) Product Preview
Alexanders Fast GPIO Access Tutorial:
BeagleBone IO using Python and mmap
There are only a limited number of physical pins to choose from, but many internal signals to put to those physical pins. Due to this limited pin count, most GPIO pins can be multiplexed to many different internal signals. In addition to internal signal selection, some pins can be configured to have pullups or pulldowns, fast or slow rise times, and as input or output pins. All of these settings are contained in a pin configuration register with one register for each pin.
Pad Control / Configuration Register
The configuration register is 32 bits wide and is the same format for all pins and does three things:
- Sets up the internal multiplexer to select an internal signal to that gets connected to the pin.
- Sets the pin to an input, otherwise it’s an output only pin.
- Connects or disconnects an internal pullup or pulldown.
The format of the configuration register is the same for all pins, and can be found in section 9.2.2, “Pad Control Registers” in the Technical Reference Manual, but here’s my version of the table:
Bringing An Internal Signal Out To A Pin
Since each pin can be connected to multiple internal signals, a multiplexer is used to select which internal signal gets brought out. Table 2-7 in the Product Preview lists all signals that can be brought out for each pin, and the MUXMODE value that needs to be placed in the pins configuration register to bring that signal out. For the beaglebone, the pins leading to the headers and the MUXMODE values to bring out all the different signals are listed in Table 9 in the BeagleBone System Reference Manual … OH JUST KIDDING, they only partially filled out the table. Most are there, but a bunch are missing, including all of the PRU-ICSS GPIO signals (which can be found here).
To route an internal signal to a GPIO pin
- Find the pin name that the internal signal routes to.
Look up the physical “pin name” that the internal signal can be muxed to in table 2-7 “Ball Characteristics” section of the Product Preview. You’ll find the internal signals listed in the “Signal Name” column, and the pin that this signal can be connected to in the “Pin Name” column. Next to the signal name will be a mode number. This is the MUXMODE value that needs to go into the pins configuration register. Write down the Pin Name and the mode number.
- Find the settings that the pin and signal support
In table 2-7, you’ll also see a “Type” and “Pullup/Down Type” column.
The Type column shows if the signal is an input, output, or both. This determines what values can be used for the RXACTIVE field of the configuration register. If I or I/O is listed, RXACTIVE can be enabled and the value will end up in some register location than can be read (see the signals details for where). Otherwise, it shouldn’t be, since the received value wont be accessible.
The pull up and down types show if there is a pull up (PU) or pull down (PD) attached to the pin. If either aren’t listed, then there’s nothing to connect, so enabling wont do anything.
I could only find one mention of slew, used for the DDR pins. I’m assuming the setting is ignored for all other pins.
- Find the configuration register to configure the pin.
The configuration registers are contained in the Control Module memory space. Each register is listed as an offset from the Control Modules starting memory address, so the final configuration register memory location will be the Control Module address + the configuration register offset.
Look up the “Control Module” memory address in the processors Memory Map in the Technical Reference Manual. For the BeagleBone with a Cortex-A8, this is 0x44E30000.
Look up the find the configuration register offset for the pin name in table 9-10, “Control_Modules Registers”, in the Technical Reference Manual. The names listed aren’t exactly the pin names, but it should be obvious. For instance, the entry for pin GPMC_A11 is conf_gpmc_a11.
Example: Lets say the signal we’re trying to get out is gpio1_27. The pin name is GPMC_A11. The Control Module start address is 0x44E30000. The configuration register for this pin is listed as conf_gpmc_a11, with an offset value listed as 0x086C. The memory location for the configuration register is 0x44E30000 + 0x086C = 0x44E3086C.
- Set the configuration register
Decide what pullup, slew, and input settings desired pull up/down settings and select the mode to the value found in step 1. Write the configuration register…but how?
There’s a command called devmem2 that will let you read and write to any non-protected memory locations. “Unfortunately”, the GPIO configuration bits are in kernel space, so require privileged (kernel) mode (thanks Alexander). This means you’ll have to make a kernel module, or use file system routines to set the registers. As Alexanders tutorial points out, it’ll look something like
echo <value> > /sys/kernel/debug/omap_mux/<pin name>
where <value> is the value to put into the configuration register for the <pin name>.
If the pin had output capabilities, it should track your internal signal value. If the pin had input capabilities, and you enabled it, you should be able to read the pins state through the signals read memory address.
High speed toggle rate
If you need something high speed and deterministic (known timing), you can use the PRU GPIO pins. With these, 200MHz is achievable, with the availability of a free 200MHz 28-bit shift register and PWM built in!
Other BeagleBone Tutorials
Errors? Something unclear? Leave a comment!