Temperature Sensor Array

Use the top metal layer of a CMOS process to build structures that resonate at a specific frequency. Use the layer below to excite the resonance. Use the layer below that to build a similar structure and use as a reference. By measuring the difference in frequency between the two, small changes/differences in the structure (like length) could be detected. If possible, coat the top layer to a dark color. Stick a lens in front of it and maybe you have an un-cooled thermal imaging system with decent sensitivity and probably pretty good response time?

The response time for heating would be a function of the thermal mass, the absorbed/long energy, and conduction through the vias. Maybe by holding the lower metal that the via is attached to at a temperature lower than the ambient or observed, better response times would be seen (by Newtonian cooling, greater temperature difference, greater rate of heat transfer).

The reference would just act as a way to make a differential measurement and, possibly, reduce the speed of the logic required since beat frequencies could be detected using mixing rather than using the fundamental of each. Localized heating (heating that warmed the whole structure, reference and detector) would most likely be somewhat widespread and slow allowing diode temperature sensors, spread all over the chip on the silicon layer, to be used to compensate.

If this ran at hundreds of MHz or GHz, this would probably be pretty sensitive.

The sensor resonant frequency would be measured capacitively, maybe by looking at the time between voltage peaks (changing the plate separation in a capacitor with a fixed charge changes the voltage) or be looking at a sweeping excitation frequency and the maximum sensor displacement (by measuring the capacitance directly.

Maybe having the excitation “plate” be a similar structure, and then looking at the beat frequency in the impedance between the two would be easier.

Some fancy deconvolution could probably be used to help get rid of the motion blur cause by the slow response time of the sensors, especially since the heating and cooling response would probably be non linear (from Newtonian cooling).

For densities…using a 0.18um CMOS process…and using a 2um minimum top metal trace width (double that to include spacing) and an aspect ratio of 5, and a 20mm by 15mm sensor, that would be something like 277 by 370 pixels (assuming square pixels). Or, for 35mm frame (34mm by 24mm), 629 by 533 pixels. This could be made greater by rearranging the sensors, using non-square pixels, or having smaller aspect ratios (which would lower sensitivity).

I assume someone is already doing this.

Edit: Here is a paper on making structures using the metal layer and etching away the silicon to free them: Experiments on the Release of CMOS-Micromachined Metal Layers. This might mean that it’s not possible to have a hanging structure in the upper metal layer…only on the lowest layer.