Idea: Cracked wafers?

Relating to the bandwidth segregated data transmission…

I picture chips 

1. |=======| - photoelectric layer
2. |=======| - charge storage
3. |=======| - adjacent storage distribution
4. |=======| - logic
5. |=======| - diode and transistor junctions (photo).

1. photoelectric layer to supply power, probably wouldn’t have to be too efficient
2. store and filter the power
3. some sort of low voltage drop rectifier to allow adjacent, power hungry, cells to continue being power hungry
4. logic - maybe a mix of fixed functional blocks and programmable logic
5. diode and transistor junctions to act as silicon pn junction leds and photodiodes 

When the wafer cracks, the diode and transistor junctions would act as data paths between the cracks. Since the power is supplied locally, each section of the crack would only need light, some surviving logic blocks to handle addressing each cracked section for handling communication (select best diode/transistor junctions, handle programming, handle data network addressing of the cracked piece, dead space identification, etc).

Maybe the bandwidth segregated communication could help quickly program the devices in the different tiers of bandwidth capability. Some bandwidth related identification could be used as well. Send some pseudo-random signal, take incremental time averages and apply a threshold to end up with a code that would help identify the sections parameters (bandwidth capabilities, addressing blocks, task assignment, etc).

For the programmable logic, I suppose it would be something like an FPGA, with functional blocks that acted as programmable logic, or more analog like a neural network.

I picture window sized pieces, with all of their flaws and cracks, computing away, covering the face of every building.

In the dream that I saw these buildings in, they were powering some AI that was governing the world…but I suppose society would probably use it for some futuristic version of Angry Birds. :)